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DetailsNets Wire BOOT1 has multiple names (Net Label BOOT1,Net Label BOOT1,Net Label PB2,Net Label PB2)
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Altiumdesigner19画原理图时如何隐藏compoNets中的PCBLIB封装哦？18是自动隐藏，19怎么隐藏哦？
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在敷铜快速选择网络时 如果选择的是焊盘与铜皮 按F11出来默认是notNet只有过孔和铜皮按f11出来有网络总结起来就是ad18敷铜时如何给铜皮快速选择网络
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PCB 进行design rule check 时报错，提示Un-Routed Net Constraint: Net V_VS Between Track (33.223mm,-13.425mm)(34.781mm,-13.425mm) on Bottom Layer And Pad R85-2(
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PCB 进行design rule check 时报错，提示Un-Routed Net Constraint: Net V_VS Between Track (33.223mm,-13.425mm)(34.781mm,-13.425mm) on Bottom Layer And Pad R85-2(
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Orphaned copper starting from : Region (0 hole(s)) Top Layer老师，这个错误是什么意思？？Net +3.3V is broken into 1 sub-Nets. Routed To 100.00% SubNet : R148-2 R150-
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